1. Field of Application
The present invention relates to a method and apparatus for data transfer and in particular to a method and apparatus for data transfer which is applicable to processing elements, whereby a plurality of processing elements can operate in combination as a multiprocessor system.
In the following description, the term "processing element" signifies a unit consisting of at least a processor (i.e. digital microprocessor), a memory and a data transfer controller, respectively coupled to internal data and address buses of the processing element.
2. Prior Art Technology
FIG. 1 shows an example of a prior art multiprocessor system, for describing a method of data transfer used in the prior art when a pair of processing elements operate in combination as a multiprocessor system. A processing element 124a is formed of a processor 1a, memory 2a, data transfer controller 130a, and data bus 4a, while a processing element 124b is formed of a processor 1b, memory 2b, data transfer controller 130b. The address buses are not shown. 5a, 5b denote respective transfer command signals produced by the processors 5a, 5b. 108a, 108b denote status counters whose count value represents the current data transfer status, i.e. which are used keep count of the number of data transfer commands which have been issued, 16a, 16b denote respective "count down" signals for decrementing the contents of these counters, 17a, 17b denote output signals representing the counter contents, and 18 denotes a network having a bus to which the processing elements 124a, 124b are connected via their respective data transfer controllers. 7a, 7b denote respective control sections of the data transfer controllers 16a, 16b.
With a multiprocessor system configured in this way, the process of transferring data from the processing element 124a to the processing element 124b can be executed as follows, assuming for example that each of a set of successive words, obtained as a processing result by the processor 1a and written into the memory 2a, is to be transferred to the processor element 124b. In this case, as each word is written into the memory 2a by the processor 1a, the processor 1a sends a transfer command signal to the data transfer controller 130a, and also sends signals to the data transfer controller 130a for setting into an address counter (not shown in the drawing) the address into which has been written the first of the words that are to be transferred, and for updating the address counter contents as each additional transfer command is issued. The data transfer controller 130a responds to each transfer command represented by the signal 5a by incrementing the count value of the counter circuit 108a (i.e. from a predetermined initial value). Thereafter, so long as the output signals 17a from the counter 108a represent a count value that is higher than the initial count, then each time that the data bus 4a becomes available (e.g. because the processing is currently executing internal processing) a data word whose address is specified by the address counter of the data transfer controller is read out of the memory 2a under the control of the data transfer controller 130a, and is supplied to the data transfer controller. When this occurs, the count value of the counter circuit 108a is decremented by one, and the address counter of the data transfer controller 130 is incremented by one. That is, the count value in the counter 108a is incremented each time a transfer command signal is generated, and is decremented each time that a data transfer subsequently occurs in response to the transfer request represented by that transfer command signal. In this way it is ensured that the number of words that are read out of the memory for data transfer will be identical the number of data transfer commands issued by the processor. The data thus supplied to the data transfer controller 130b are transferred by the data transfer controller 130b to the network 18, then to the data transfer controller 130b of the processing element 124b, to be written into the memory 2b of that processing element.
A second prior art method of data transfer for achieving multiprocessor system operation is described in Japanese Patent Laid-open No. 64-9563. FIG. 2 is a simple block diagram for describing the operation of that data transfer method. 80a, 80b denote respective processors, 20 is a dual-port memory, 21a, 22b are bus interface circuits, and 22a, 22b are sets of registers. With such a configuration, data transfer is executed in the following sequence, for the case of transferring data from the processor 80a to processor 80b. The processor 80a checks for a bit which indicates completion of readout of data from the processor 80b to the register group 22b. If that bit is asserted, then write-in to the dual-port memory 20 is started, via the bus interface circuit 21a. When write-in has been completed, an interrupt signal is sent to the processor 80b, and a bit which indicates completion of write-in via the bus interface circuit 21a of the processor 80a is asserted. The processor 80b looks for a signal indicating completion of write-in to the processor groups 22a, 22b by the processor 80a, and when it finds that this signal is asserted, the processor 80b begins read-out of data from the memory 20 via the bus interface circuit 21b.
However with such prior art data transfer methods, several problems will arise. Specifically, in the case of the first prior art method described above, data transfer into a processing element or out from a processing element is only possible during intervals in which the data bus 4 (and address bus) of that processing element are released (i.e. when the processor of the processing element is not currently accessing the memory). If there is a high probability of the internal buses being free at any given time, then it will generally be possible for the data transfer controller, each time that a transfer command signal is issued by the processor, to access the memory soon after that (i.e. at the first occasion when the data and address buses are released by the processor) in order to read out of the memory data that are to be transferred out of the processing element, or to write into the memory data that have been transferred into the processing element from the other processing element. However in a practical multiprocessor system (and in particular in the case of a system which is used for high-speed real time simulation, which is the most important application of multiprocessor systems) the frequency of memory accessing by the processor of each processing element of the multiprocessor system is extremely high. Thus, the internal data and address buses of each processing element will rarely be in a free condition, so that it will be necessary for each data transfer to wait until the internal buses become free. Moreover in multiprocessor system applications such as simulation, the desired rate of data transfer operations can be extremely high, so that time required to execute data transfers will have an adverse effect on the overall system performance. As a result, even if the individual processing elements incorporate high speed processors, it is difficult to achieve the levels of performance that can be envisaged for such a multiprocessor system.
In the case of the second prior art method of data transfer described above, the amount and complexity of hardware required will be excessive, due to the incorporation of the dual-port memory. The difficulties which arise in implementing and controlling a dual-port memory are well known, and use of such a device is undesirable, even in the case of a multiprocessor system which contains only two processors. Moreover due to the fact that data transfers are executed via the dual-port memory, it would be necessary to configure a special memory configuration for a multiprocessor system having a larger number of processors than two, and that would be extremely difficult to accomplish.